Summary of "Introduction to IC Packaging Technology"
- Categories:媒体报道
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- 2015.06.03
(Summary description)The packaging process is relatively complicated, there are about a dozen processes, including grinding and dicing... Grinding is to thin the back of the wafer to meet the needs of packaging; dicing is to use a metal blade to allow the wafer to be Divide them one by one; chip mounting is to use conductive glue to fix the chip and lead frame; bonding is to achieve circuit conduction between the pad of the chip and the frame; plastic packaging is to package the product.
Summary of "Introduction to IC Packaging Technology"
- 2015-06-03






























Q&A discussion session:
1. Student Chen: What does the thickness of the grinding disc have to do with? What is the minimum width of the saw blade now?
package size. After consulting our scribing engineer, our company can achieve a minimum of 60um at present.
2. Classmate Wen: What is the most challenging step in the packaging process shared today?
WB (Wire Bonding bonding process). Mainly include high package integration, wire density, wire punching after plastic sealing, whether the wire hits the Pad silicon layer, wire arc length control, and WB pull, thrust, and lMC control. The other is the encapsulated layered control and system engineering.
3. Zheng: Can epoxy resin be applied by printing?
It should be said that CoB encapsulation, point black glue curing, possibly by printing. This can be answered by Mr. Ye, the sales director of Zhongpeng Plastics in the group, and material experts.
4. Ye: How long does it usually take to cure? After seeing a small factory, the curing time is only 2 hours. What is the impact of the short time?
The pre-curing generally adds N2 for one hour, and the post-curing is traditionally 6 to 8 hours. The specific reference material TDS. Short post-cure times result in insufficient stress relief and compromised reliability.
5. Classmate Ye: Can the scribing angle be measured?
The scribing has a jumping angle. Generally, if it is not detected, there will be leakage during the measurement. When dicing the edge, it depends on the function of the iC and the specific position and size of the corner. Generally speaking, large corners are not allowed, which will cause reliability failure, and the measurement may be stuck or missed. We have encountered product test idd failure, and it has been confirmed by the rot-opening test that the leakage failure is caused by the scribing angle.
6. Student Chen: Which of these process steps will be high temperature? Will the maximum temperature exceed 400 degrees?
Due to the relationship between the welding wire and the chip, the copper wire is generally slightly higher than the gold wire. Generally, it is controlled at 180 to 240 degrees in the main welding area, MD is controlled at about 175 ± 5 degrees, and eutectic is controlled at about 400 degrees.
7. Student Zheng: Does the eutectic refer to the ball seal?
No, the eutectic is the combination of the bracket and the wafer chip back gold form DB, and the BGA refers to the ball seal.
8. Classmate Ye: When is the eutectic and what is the soldering condition? Does the eutectic need to be wired?
The eutectic is the combination of the bracket and the back gold form of the wafer chip. The solder is generally suitable for T0 high-power devices and is easy to dissipate heat. During DB, the scaffold is eutectic bonded to the wafer. Eutectic is DB, WB is wire bonding, flip chip does not need wire bonding.
9. Luo: Can the packaging and testing equipment be localized? Is there anything that can't be done?
Packaging and testing equipment and materials are being localized. Most of the domestic equipment and materials can reach the industry's technological level and can basically achieve industrialization.
10. Zheng: Is the cost of packaging high? For example, the proportion of ic cost?
1) Refer to the approximate ratio of the packaging cost of DRAM CSP and WLCSP to the chip cost that a student searched from the Internet.

2) This problem is related to different product lines. Some consumer products use direct cob, which saves money on plastic packaging and is less reliable. A classmate gave an example of an optoelectronic chip: the chip cost of an optoelectronic chip is $1, the packaging cost may be $100, and then it is sold for $200. Probably not the same cost composition as most chips. As long as the package is delivered, the cost of ceramic packaging is acceptable, and the golden box is the most expensive. Some chips are delivered as bare chips, and then the system side packages many chips together to reduce the packaging cost.
11. Zheng: Under what circumstances do you choose dicing packaging? When would wafer level packaging be considered?
The difference between WL-CSP and the traditional packaging method is that the traditional chip packaging is first cut and then sealed and tested, and after packaging, the size of the original chip is increased by about 20%; while WL-CSP is first on the whole wafer. Therefore, the packaged volume is almost the same as the IC bare chip size, which can greatly reduce the packaged IC size.
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