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Introduction to IC Packaging Technology
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Origin:
2015.06.03
The packaging process is relatively complex, with about a dozen steps, including grinding, dicing... Grinding is to thin the back of the wafer to meet packaging needs; dicing is to use a metal blade to separate the wafer into individual chips; die attach is to fix the chip to the lead frame using conductive adhesive; bonding is to achieve circuit connectivity between the chip's pads and the frame; encapsulation is to package the product. The key processes are 'bonding and encapsulation', where bonding achieves our purpose, and encapsulation ensures quality assurance and product reliability for bonding.
Q&A Discussion Session:
1. Chen: What is the relationship between grinding thickness and what? What is the minimum width of the saw blade now?
Packaging size. I consulted our dicing engineer, and currently, our minimum can reach 60um.
2. Wen: Which step in today's shared packaging process is the most challenging?
WB (Wire Bonding) process. It mainly involves high integration in packaging, dense wires, whether the wire bonds reach the pad silicon layer after encapsulation, control of wire arc length, as well as WB pull force, push force, and lMC control. Additionally, there is layered control of packaging, which is a system engineering.
3. Zheng: Can epoxy resin be applied by printing?
It should be said that CoB packaging can cure black glue through printing. This can be answered specifically by Mr. Ye, the sales director of Zhongpeng Plastics in our group, who is a material expert.
4. Ye: How long does curing generally take? I saw a small factory where curing only took 2 hours; what impact does a short time have?
Pre-curing generally adds N2 for one hour, while post-curing traditionally takes 6-8 hours; refer to material TDS for specifics. Short post-curing time can lead to insufficient stress release and affect reliability.
5. Ye: Can dicing corner bumps be detected?
If there are corner bumps in dicing and they are generally not detected, there may be leakage during testing. Dicing edge bumps depend on the IC's effectiveness and the specific location and size of the bumps; generally speaking, large corner bumps are not allowed as they can cause reliability failures. Testing may get stuck or miss detection; previously we encountered product testing IDD failures confirmed by corrosion tests caused by dicing corner bumps leading to leakage failure.
6. Chen: Among these process steps, which ones involve high temperatures? Will the maximum temperature exceed 400 degrees?
WB due to solder wire and chip relationships; copper wire is generally slightly higher than gold wire, usually controlled at 180-240 degrees in the main solder area, with MD controlled around ±5 degrees at about 175 degrees, and eutectic controlled around 400 degrees.
7. Zheng: Does eutectic refer to ball bonding?
No, eutectic refers to the combination of a bracket with a back-gold form of wafer chip DB; BGA refers specifically to ball bonding.
8. Ye: When does eutectic occur and under what circumstances for solder? Does eutectic still require wire bonding?
Eutectic refers to the combination of a bracket with a back-gold form of wafer chip DB; solder is generally suitable for T0 high-power devices that are easy to dissipate heat. It is one of several implementation processes for DB related to chip structure function and packaging form realization. In DB, the bracket combines with the wafer through eutectic bonding. Eutectic is DB; WB refers to wire bonding; flip-chip does not require wire bonding.
9. Luo: Have all packaging test equipment been localized? Is there anything that cannot be done yet?
Packaging test equipment and materials are being localized; most domestic equipment and materials can meet industry process standards and can basically achieve industrialization.
10. Zheng: Is the cost of packaging high? For example, what proportion does it occupy in IC costs?
(1) Referencing a classmate's online search results on the approximate cost ratio of DRAM CSP and WLCSP packaging costs to chip costs.
(2) This question relates to different product lines; some consumer products use direct CoB packaging, saving on encapsulation costs but with slightly lower reliability. A classmate cited an example of optoelectronic chips: The chip cost for optoelectronic chips is $1, while packaging costs may reach $100, then selling for $200. This may differ from most chip cost compositions. As long as packaging delivery occurs, ceramic packaging costs are acceptable; golden box packaging is the most expensive. Some chips are delivered as bare dies, then system parties package many chips together to reduce packaging costs.
11. Zheng: Under what circumstances would you choose dicing packaging? When would you consider wafer-level packaging?
WL-CSP differs from traditional packaging methods in that traditional chip packaging involves cutting before testing; after packaging, it increases by about 20% compared to original chip size; whereas WL-CSP packages and tests on an entire wafer before dicing it into individual chips, thus maintaining almost the same volume as IC bare chip size after packaging significantly reduces IC size.
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