Hang Shun HK32F103A empowers smart cat litter box, starting the "core" level empowerment preferential plan

I. Market Size and Growth 

In recent years, with the improvement of people's living standards and the booming development of the pet industry, the number of pet cats has been increasing, and the market demand for smart cat litter boxes has shown a rapid growth trend. According to market research institutions, the global market size of smart pet products is expected to reach 2025  in 367 US dollars, and smart cat litter boxes, as one of the essential daily necessities for pet cats, have huge market potential, with a compound annual growth rate expected to exceed 7%。

II. Market Applications 

Home Scenarios: Smart cat litter boxes have become the first choice for many cat-owning families. Their automatic scooping and deodorizing functions provide great convenience for cat owners, saving them time and effort in cleaning cat litter, allowing them to focus more on work and life. 

Pet Shops and Veterinary Hospitals: Pet shops can use smart cat litter boxes to provide a comfortable living environment for cats in foster care, improving service quality and competitiveness. Veterinary hospitals can use them for the care of hospitalized cats, allowing medical staff to understand the cat's excretion situation at any time, and better monitor and care for the condition. 

Cat Boarding Houses: The large demand for cat boarding requires boarding houses to be equipped with efficient and convenient cat litter box cleaning equipment. Smart cat litter boxes can automatically clean and deodorize, reducing manual cleaning workload and providing cats with a clean and hygienic living environment to meet the daily operational needs of boarding houses. 

III. Solution Overview 

Hang Shun HK32F103A is a high-performance based on the ARM Cotex-M3 core MCU with a maximum clock frequency of 120MHz , featuring high performance, high integration, and low power consumption. It has rich peripheral interfaces, such as UART 、 SPI 、I2C、 PWM , allowing easy connection and control of various sensors and actuators. Based on Hang Shun’s HK32F103A smart cat litter box solution, by integrating multiple sensors such as weight sensors, infrared sensors, and odor sensors, it can achieve real-time monitoring of cat excrement in the litter box. When cat excretion is detected, the motor is automatically controlled to operate, driving the scooping device to clean the feces to a designated location, and removing odors through the built-in deodorizing device. At the same time, this solution can also be equipped with Wi-Fi or Bluetooth modules to connect with mobile phone APP , allowing users to remotely view the status of the cat litter box anytime, anywhere through their mobile phones, such as the remaining capacity, deodorizer remaining amount, etc., and remotely control various functions of the cat litter box, such as starting cleaning, adding deodorizer, etc. 

IV. Core Advantages of the Solution 

(1) High-Performance Computing Power: Hang Shun HK32F103A The 120MHz main frequency and up to 512KB The Flash and 64KB The SRAM can meet the real-time computing needs of complex algorithms for smart cat litter boxes, such as the rapid processing and analysis of sensor data, ensuring accurate monitoring and timely response of the litter box. 

(2) Rich Peripheral Interfaces: Its various peripheral interfaces allow easy connection with various sensors, motor driver chips, communication modules, etc., eliminating the need for additional expansion chips, reducing hardware costs and design complexity, and improving system integration and reliability. 

(3) Low-Power Design: This chip has multiple low-power modes, and reasonable configuration can allow the smart cat litter box to maintain low power consumption in standby mode, extending the product's service life and meeting environmental protection and energy-saving requirements. 

(4) High Reliability: The operating temperature range is -40 ℃ ~105 ℃, with industrial-grade ESD protection capabilities, allowing stable operation in various harsh environments and ensuring long-term reliable use of the smart cat litter box. 

(5) Advantages of Domestic Substitution: Fully compatible with foreign F103 series chips, supporting seamless code migration, reducing development costs and risks, and helping to promote the independent and controllable development of the domestic smart cat litter box industry. 

Product System Block Diagram 

Physical Diagram 

Hang Shun HK32F103A Series MCU Main Specifications 

• ARM® Cortex®-M3 Core 
• Maximum Clock Frequency: 120 MHz
• 24  bit System Tick Timer 
• Support CPU Event Signal Input to MCU pins, enabling interaction with other components on the board Soc CPU interaction. 
• Operating Voltage Range 
• Dual Power Domains: 
• - Main Power VDD is 2.0 V ~ 3.6 V 
• - Backup Power VBAT is 1.8 V ~ 3.6 V 
• When the main power is off, RTC can continue to operate under VBAT power. 
• VBAT The power domain provides 84 bytes of backup registers. 
• Operating Temperature Range: -40 ° C ~ +105 ° C 
• VDD Typical Operating Current 
• Run Run mode: 19.3 mA@120MHz@3.3V 
• Sleep Sleep mode: 5.6mA@120MHz@3.3V (Wake-up time: 1  machine clock cycles) 
• Stop Stop mode 
• - LDO Low-power mode: 89.4  μ A@3.3V (Wake-up time: 10µs ) 
• - LDO Full-speed operating mode: 303  μ A@3.3V 
• Standby Standby mode: 3.3  μ A@3.3V (Wake-up time: 150µs ) 
• VBAT Typical operating current ( VDD power down) 
• VBAT RTC ON mode: 2.6  μ A@3.3V 
• VBAT RTC OFF mode: 2.1  μ A@3.3V 
• Memory 
• Maximum 512 Kbytes The Flash Memory 
• -  When CPU main frequency is no higher than 24 MHz , supports 0  wait bus cycles. 
• -  It has code security protection, and read and write protection can be set separately. 
• 64 Kbytes Internal SRAM 
• FSMC module can be externally connected to 1 Gbyte NOR/PSRAM/NAND/PC Card memory (of which, 256 Mbytes of space can store instructions and can be used for internal Cache cache) 
• Data Security 
• CRC32 checksum hardware unit 
• Clock 
• External high-speed clock ( HSE ): Supports 4 ~ 32 MHz , typical 8 MHz
• External low-speed clock ( LSE ): 32.768 kHz 
• Internal high-speed clock ( HSI ): 8 MHz/28 MHz/56 MHz Configurable 
• Internal low-speed clock ( LSI ): 40 kHz
• PLL output clock: 120MHz (Maximum) 
• GPIO External input clock: 1 ~ 64 MHz 
• Reset 
• External Pin Reset 
• Power Reset ( POR/PDR ) 
• Software Reset 
• Watchdog ( IWDG and WWDG ) Reset 
• Low-Power Management Reset 
• Programmable Voltage Detector ( PVD ) 
• 8  Adjustable detection voltage threshold 
• Rising and falling edge detection configurable 
• General Purpose Input Output Port ( GPIO ) 
• 64  Package provides 51  number GPIO pins, 100  Package provides 80  number GPIO pins 
• All GPIO Pins can be configured as external interrupt inputs 
• Built-in switchable pull-up/pull-down resistors 
• Supports open-drain ( Open-Drain ) output 
• Supports Schmitt ( Schmitt ) hysteresis input 
• Output drive capability selectable in four levels: ultra-high, high, medium, and low 
• Data communication interface 
• 5  number USART/UART ( USART1/2/3，UART4/5 ) 
• 3  number SPI ( SPI2/3 Supports I2S protocol) 
• 2  number I2C
• 1  number SDIO 
• 1  number CAN 2.0 A/2.0B 
• 1  number full-speed USB2.0
• Timer and PWM Generator 
• Advanced Timer: TIM1/TIM8 (with dead-time complementary PWM output) 
• General Purpose Timer: TIM2/TIM3/TIM4/TIM5
• Basic Timer: TIM6/TIM7 (supports CPU interrupt, DMA request and DAC conversion trigger) 
• On-chip analog circuits 
• 3  number 12  bit 1 MSPS ADC (supports up to 16  number external analog input channels simultaneously; including 2  number weak drive signal input channels and 1  number 5 V high-voltage signal input channels); supports dual ADC mode, sampling rate up to 2 MSPS。
• 2  number 12  bit DAC 
• 1  temperature sensors 
• 1  number 0.8 V Internal reference voltage source 
• 1  number VBAT Power resistor divider (divider output connected on-chip with ADC to achieve VBAT power voltage monitoring) 
• DMA Controller 
• 2  number independent DMA ： DMA1 and DMA2
• DMA1 Provides 7  number channels 
• DMA2 Provides 5  number channels 
• Support Timer 、 ADC 、 SPI 、I2C、 USART 、 UART and other peripheral triggers 
• CPU Debug and trace interface 
• SW-DP Two-wire debug port 
• JTAG Five-wire debug port 
• ARM DWT 、 FPB 、 ITM 、 TPIU Debug trace module 
• Single-wire asynchronous trace data output interface ( TRACESWO ) 
• Four-wire synchronous trace data output interface ( TRACEDO[3:0] 、 TRACECKO ) 
• Custom DBGMCU Debug controller (low-power mode simulation control, debug peripheral clock control, debug and trace interface allocation) 
• RTC Clock counter, used with software to record year, month, day, hour, minute, and second 
• ID Identifier 
• Each chip provides a unique 96  bit ID Identifier 
• Reliability 
• Through HBM2000V/CDM500V/MM200V/LU200mA Level testing

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